Leakage power has been described as the most critical challenge facing designers of advance chips today. At 90nm, 30% of a chip’s total power consumption may be attributed to leakage. At 65nm, leakage represents over 50% of a chip’s total power consumption and this trend will continue at 45nm and beyond.
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Monday, December 3, 2007
Tuesday, November 13, 2007
Control Leakage In Active Mode
Control of subthreshold leakage in standby mode is best accomplished with power-shutoff switches. But what can be done when the chip is fully awake and active?
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Stanch The Bleeding Of Leakage Power At 65nm
Even as leakage overwhelms their power budgets, IC design teams are finding ways to plug the holes that are costing them dearly at sub-micron nodes.
As 90-nm process technologies began entering the mainstream a few years ago, it became clear that device delays were no longer the chief culprit. Interconnect delays had caught and passed them, becoming the number-one contributor to timing woes.
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As 90-nm process technologies began entering the mainstream a few years ago, it became clear that device delays were no longer the chief culprit. Interconnect delays had caught and passed them, becoming the number-one contributor to timing woes.
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Monday, November 5, 2007
Blaze DFM Lithography-Aware Design Optimization Demo Now Available
Exclusive Preview of New Blaze MO Capabilities Available at Demos on Demand
Blaze DFM, the electrical DFM company, has created an online demonstration previewing new lithography-aware capabilities that will become available in the next release of the Blaze MO™ leakage power optimization software.
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Blaze DFM, the electrical DFM company, has created an online demonstration previewing new lithography-aware capabilities that will become available in the next release of the Blaze MO™ leakage power optimization software.
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Thursday, October 18, 2007
Modeling, Simulation Gear Up to Meet Next-Generation Needs
Producing a working chip design has been getting increasingly complicated since the days of rubilith and Xacto knives. We live in an era in which circuit quantum effects complicate the lives of designers performing advanced work. EDA tool have come to the rescue, which provide the means to verify the increasingly complex chip designs, ensure that they will function as intended, and play “what if” games for the next technology node.
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Wednesday, September 19, 2007
Industry coalition seeks to advance DFM
A group of chip makers and EDA tool vendors have formed a design-for-manufacturing (DFM) coalition intended to build on previous DFM efforts. Blaze DFM will contribute a proposed standard for the interaction between chip design tools and lithography simulation engines.
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Tuesday, September 18, 2007
Hot Chips, Cool Books, Brainiacs & Workaholics Abound
Synergy notwithstanding, Dave Reed, Vice President of Marketing & Business Development at Blaze DFM, offered answers by email to the following questions regarding the Cadence/Clear Shape deal.
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Si2 Announces New Design-For-Manufacturability Coalition
Major Technology Contribution Received from Ponte Solutions and Blaze DFM
Silicon Integration Initiative (Si2) today announced the formation of the Design-For-Manufacturability Coalition (DFMC) which will build on previous efforts to ensure that ICs can be manufactured in accordance with the original design. Founding members include Cadence, Freescale Semiconductor, IBM, Ponte Solutions, Samsung, Sagantec, ST Microelectronics, and Texas Instruments.
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Silicon Integration Initiative (Si2) today announced the formation of the Design-For-Manufacturability Coalition (DFMC) which will build on previous efforts to ensure that ICs can be manufactured in accordance with the original design. Founding members include Cadence, Freescale Semiconductor, IBM, Ponte Solutions, Samsung, Sagantec, ST Microelectronics, and Texas Instruments.
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Monday, September 17, 2007
Ponte Solutions and Blaze DFM Deliver Yield and Litho Modeling Elements to Si2 Specification, 9/17/07
Ponte Solutions(TM), the bridge between design and manufacturing, and Blaze DFM, the electrical DFM company, today announced delivery of the first modeling elements committed to Si2's Design For Manufacturability Coalition (DFMC) last year. These contributions are the primary drivers for the critical area analysis and lithography elements of Si2's DFMC efforts.
Ponte Solutions(TM), the bridge between design and manufacturing, and Blaze DFM, the electrical DFM company, today announced delivery of the first modeling elements committed to Si2's Design For Manufacturability Coalition (DFMC) last year. These contributions are the primary drivers for the critical area analysis and lithography elements of Si2's DFMC efforts.
Thursday, September 13, 2007
How low can you go? A look at 45-nm-IC-design challenges, EDN 9/13/07
If you have tools for the 65-nm or even the 90-nm node, moving to the 45-nm node requires no retooling. But designers moving to this node must adopt some advanced design techniques and be aware of some new design rules that foundries have imposed to ensure that SOC designs yield acceptable results.
If you have tools for the 65-nm or even the 90-nm node, moving to the 45-nm node requires no retooling. But designers moving to this node must adopt some advanced design techniques and be aware of some new design rules that foundries have imposed to ensure that SOC designs yield acceptable results.
Tuesday, September 4, 2007
Are EDA Companies Getting Fair Value for their Software? EDA Weekly 9/3/07
An interview with Jacob Jacobsson, CEO of Blaze DFM. The company has a product, Blaze MO, which significantly reduces leakage power and thereby improves parametric yield. Near the end of the interview we discussed the issue of whether Blaze and by extension other EDA companies were deriving the appropriate amount of value for the benefits their products and services provide to their customers.
An interview with Jacob Jacobsson, CEO of Blaze DFM. The company has a product, Blaze MO, which significantly reduces leakage power and thereby improves parametric yield. Near the end of the interview we discussed the issue of whether Blaze and by extension other EDA companies were deriving the appropriate amount of value for the benefits their products and services provide to their customers.
Tuesday, August 7, 2007
STARC Settles On A 65-nm Lithography Simulator/Analyzer, Electronic Design 8/6/07
Following a three-month evaluation, the Semiconductor Technology Academic Research Center (STARC) has tabbed Blaze DFM’s Halo for lithography simulation and analysis. The tool will be integrated into STARC’s STARCAD-CEL (Certified Engineering Linkage) reference design flow.
Following a three-month evaluation, the Semiconductor Technology Academic Research Center (STARC) has tabbed Blaze DFM’s Halo for lithography simulation and analysis. The tool will be integrated into STARC’s STARCAD-CEL (Certified Engineering Linkage) reference design flow.
Monday, August 6, 2007
STARC が米 Blaze DFM 社の新製品「Blaze Halo」を STARCAD-CEL に採用, EDA Express 8/2/07
2007年8月2日、電気的なYield最適化を行うDFMツール「Blaze MO」を手掛ける米Blaze DFMは、同社の新製品「Blaze Halo」がSTARCのリファレンスデザインフローSTARCAD-CELに採用された事を発表した。
2007年8月2日、電気的なYield最適化を行うDFMツール「Blaze MO」を手掛ける米Blaze DFMは、同社の新製品「Blaze Halo」がSTARCのリファレンスデザインフローSTARCAD-CELに採用された事を発表した。
Thursday, August 2, 2007
Blaze DFM Selected by STARC for 65nm Lithography Simulation and Analysis, 8/2/07
Blaze DFM, the electrical DFM company, has been chosen by the Semiconductor Technology Academic Research Center (STARC) to provide lithography simulation and analysis software that will be integrated into the STARCAD-CEL (Certified Engineering Linkage, one step ahead of DFM) reference design flow.
Blaze DFM, the electrical DFM company, has been chosen by the Semiconductor Technology Academic Research Center (STARC) to provide lithography simulation and analysis software that will be integrated into the STARCAD-CEL (Certified Engineering Linkage, one step ahead of DFM) reference design flow.
Blaze DFM deploys SoftJin software components to speed time-to-market, 7/2/07
“Wherever possible, we leverage existing technology and infrastructure. That’s what drove our selection of the OpenAccess database and our licensing of EDA software components from SoftJin. This approach enabled us to deliver our first product, Blaze MO leakage power optimization software, in less than 18 months.” - Dr. Steffen Rochel, vice-president of engineering
Monday, July 23, 2007
Semicon panel: Design-for-manufacturability no longer a luxury, EE Times 7/23/07
SAN FRANCISCO — As the semiconductor industry tries to resolve design-for-manufacturability (DFM) issues, it can learn from the history of design-for-test, a panel of EDA gurus observed here at Semicon West.
SAN FRANCISCO — As the semiconductor industry tries to resolve design-for-manufacturability (DFM) issues, it can learn from the history of design-for-test, a panel of EDA gurus observed here at Semicon West.
EE Times updates list of emerging startups, EE Times 6/28/07
Blaze DFM, Inc. (Sunnyvale, Calif.), founded in October 2004, provides software to support "electrical DFM" and parametric yield for sub-100-nm circuits. The company landed $10 million in series B venture capital funding in March 2007 while also disclosing completion of its previously announced merger with Aprio Technologies Inc.
Blaze DFM, Inc. (Sunnyvale, Calif.), founded in October 2004, provides software to support "electrical DFM" and parametric yield for sub-100-nm circuits. The company landed $10 million in series B venture capital funding in March 2007 while also disclosing completion of its previously announced merger with Aprio Technologies Inc.
Application of DFM during IP Development Pays Big Dividends, Chip Design 6/21/07
A complete design for manufacturability (DFM) solution is made up of elements affecting many different parts of the overall design process. One of the ways in which DFM techniques can have the greatest impact on today's large chip designs is to improve the manufacturability of intellectual property (IP) blocks such as standard cells, processor cores, memories and other hard blocks.
A complete design for manufacturability (DFM) solution is made up of elements affecting many different parts of the overall design process. One of the ways in which DFM techniques can have the greatest impact on today's large chip designs is to improve the manufacturability of intellectual property (IP) blocks such as standard cells, processor cores, memories and other hard blocks.
No GAPs left behind, Electronic Supply & Manufacturing 6/1/07
OEMs can eliminate potential product performance problems early by encouraging the use of rigorous design-for-manufacturability processes at semiconductor makers.
OEMs can eliminate potential product performance problems early by encouraging the use of rigorous design-for-manufacturability processes at semiconductor makers.
Friday, July 20, 2007
La jeune pousse américaine Blaze DFM lance un outil de DFM « électrique », Electronique International 5/22/06
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