E-DFM - The Future of Parametric Yield Success

Mentor Graphics officially jumps onto the electrical DFM bandwagon created by Blaze.

At 45nm, yields exhibit drastic drop-offs, and designs fail to consistently achieve their technical and competitiveness objectives. As more and more features are placed into smaller and smaller spaces, the unintended effects of this “crowding” are creating havoc with yield and performance. The tools we have today simply aren’t designed to recognize and resolve these issues.

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Where’s the ROI in DFM?

To most designers the answer to the question “Where is the ROI in DFM?” remains somewhat illusive. But panelists at last week’s DesignCon 2008 said that as more designs move to advanced processes, the return on DFM investment will become evident as DFM will become mandatory.

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Is DFM a vitamin or a cure?

In a DesignCon 2008 panel entitled "Where is the ROI for DFM?" design for manufacturability was likened to a vitamin – it doesn’t hurt and it might do you good. So, what is the reality? Is DFM a vitamin or a cure? To find out, we report on the panel’s deliberations, as well as on a separate interview with one of the panelists, the leader of Freescale’s corporate DFM initiative.

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EDA CEOs see opportunity despite recession fears

A global recession may be unfolding, but the EDA industry will continue to do well because of the value it provides to an increasingly fabless semiconductor industry, according to EDA CEOs at an EDA Consortium "forecast panel" here Thursday (Feb. 7). But speakers also acknowledged pricing pressure and project delays.

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EE Times updates list of emerging startups

The EE Times 60 Emerging Startups list, first published in April 2004, has been updated to version 7.0 to reflect the latest corporate, commercial, technology and market conditions.

Some companies have dropped off the list — otherwise known as the Silicon 60 — because they have been acquired; some have moved on to an initial public offering of shares; and others have moved beyond the list with the passage of time.

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Driven By Power Concerns, DFM Goes Mainstream In 2008

Due to the growth in the consumer and wireless markets, low-power design is becoming a pervasive driver in IC design, verification, and implementation. The challenge lies in achieving timing closure while adopting advanced low-power and mixed-signal techniques—while improving time-to-volume and yield.

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